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single, 12-/14-/16-bit nano dac with 5 ppm/c on-chip reference in sot-23 ad5620/ad5640/ad5660 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2010 analog devices, inc. all rights reserved. features low power, single nano dacs ad5660: 16 bits ad5640: 14 bits ad5620: 12 bits 12-bit accuracy guaranteed on-chip, 1.25 v/2.5 v, 5 ppm/c reference tiny 8-lead sot-23/msop packages power-down to 480 na @ 5 v, 200 na @ 3 v 3 v/5 v single power supply guaranteed 16-bit monotonic by design power-on reset to zero/midscale 3 power-down functions serial interface with schmitt-triggered inputs rail-to-rail operation sync interrupt facility applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators product highlights 1. 12-/14-/16-bit nano dac12-bit accuracy guaranteed. 2. on-chip, 1.25 v/2.5 v, 5 ppm/c reference. 3. available in 8-lead sot-23 and 8-lead msop packages. 4. power-on reset to 0 v or midscale. 5. 10 s settling time. table 1. related device part no. description ad5662 2.7 v to 5.5 v, 16-bit dac in sot-23, external reference functional block diagram ad5620/ad5640/ad5660 v refout gnd ref(+) v dd resistor network power-down control logic dac register power-on reset 1.25/2.5v ref output buffer 16-bit dac input control logic v out v fb sync sclk din 04539-001 figure 1. general description the ad5620/ad5640/ad5660, members of the nano dac? family of devices, are low power, single, 12-/14-/16-bit, buffered voltage-out dacs and are guaranteed monotonic by design. the ad5620/ad5640/ad5660-1 parts include an internal, 1.25 v, 5 ppm/c reference, giving a full-scale output voltage range of 2.5 v. the ad5620/ad5640/ad5660-2-3 parts include an internal, 2.5 v, 5 ppm/c reference, giving a full-scale output voltage range of 5 v. the reference associated with each part is available at the v refout pin. the parts incorporate a power-on reset circuit to ensure that the dac output powers up to 0 v (ad5620/ad5640/ad5660-1-2) or midscale (ad5620-3 and ad5660-3) and remains there until a valid write takes place. the parts contain a power-down feature that reduces the current consumption of the device to 480 na at 5 v and provides software-selectable output loads while in power-down mode. the power consumption is 2.5 mw at 5 v, reducing to 1 w in power-down mode. the ad5620/ad5640/ad5660 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. for remote sensing applications, the output amplifiers inverting input is available to the user. the ad5620/ad5640/ad5660 use a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and is compatible with standard spi?, qspi?, microwire?, and dsp interface standards.
ad5620/ad5640/ad5660 rev. f | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? product highlights ........................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ad5620/ad5640/ad5660-2-3 .................................................. 3 ? ad5620/ad5640/ad5660-1 ...................................................... 5 ? timing characteristics ................................................................ 7 ? absolute maximum ratings ............................................................ 8 ? esd caution .................................................................................. 8 ? pin configurations and function descriptions ........................... 9 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 16 ? theory of operation ...................................................................... 17 ? d/a section ................................................................................. 17 ? resistor string ............................................................................. 17 ? internal reference ...................................................................... 17 ? output amplifier ........................................................................ 17 ? serial interface ............................................................................ 17 ? input shift register .................................................................... 18 ? sync interrupt .......................................................................... 18 ? power-on reset .......................................................................... 19 ? power-down modes .................................................................. 19 ? microprocessor interfacing ....................................................... 19 ? applications information .............................................................. 21 ? using a ref19x as a power supply for the ad5620/ad5640/ad5660 ....................................................... 21 ? bipolar operation using the ad5660 ..................................... 21 ? using the ad5660 as an isolated, programmable, 4 ma to 20 ma process controller ......................................................... 22 ? using the ad5620/ad5640/ad5660 with a galvanically isolated interface ........................................................................ 22 ? power supply bypassing and grounding ................................ 23 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 25 ? revision history 12/10rev. e to rev. f changes to ordering guide .......................................................... 25 7/10rev. d to rev. e moved using the ad5660 as an isolated, programmable, 4 ma to 20 ma process controller section ........................................... 22 moved power supply bypassing and grounding section ......... 23 changes to ordering guide .......................................................... 25 3/10rev. c to rev. d changes to ordering guide .......................................................... 24 10/09rev. b to rev. c changes to ordering guide .......................................................... 23 5/06rev. a to rev. b updated formatted ............................................................ universal updated temperature range ............................................ universal changes to table 2 ............................................................................. 3 changes to table 5 ............................................................................. 8 replaced figure 17, figure 18, and figure 19 ............................. 12 changes to ordering guides .................................................. 23, 24 9/05rev. 0 to rev. a changes to specifications ................................................................. 5 changes to outline dimensions .................................................. 23 7/05revision 0: initial version
ad5620/ad5640/ad5660 rev. f | page 3 of 28 specifications ad5620/ad5640/ad5660-2-3 v dd = 4.5 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd, c refout = 100 nf; all specifications t min to t max , unless otherwise noted. table 2. parameter a grade 1 b grade 1 c grade 1 unit conditions/comments static performance 2 ad5660 resolution 16 16 16 bits min relative accuracy 32 16 16 lsb max differential nonlinearity 1 1 1 lsb max guaranteed monotonic by design ad5640 resolution 14 14 14 bits min relative accuracy 8 4 4 lsb max differential nonlinearity 0.5 0.5 0.5 lsb max guaranteed monotonic by design ad5620 resolution 12 12 12 bits min relative accuracy 6 1 1 lsb max differential nonlinearity 0.25 0.25 0.25 lsb max guaranteed monotonic by design zero-code error 2 2 2 mv typ all 0s loaded to dac register 10 10 10 mv max offset error 10 10 10 mv max full-scale error ?0.15 ?0.15 ?0.15 % fsr typ all 1s loaded to dac register 1 1 1 % fsr max gain error 1.5 1.5 1.5 % fsr max zero-code error drift 2 2 2 v/c typ gain temperature coefficient 2.5 2.5 2.5 ppm typ of fsr/c dc power supply rejection ratio ?75 ?75 ?75 db typ dac code = midscale; v dd = 5 v 10% output characteristics 3 output voltage range 0 0 0 v min v dd v dd v dd v max output voltage settling time 8 8 8 s typ ? to ? scale change settling to 2 lsb 10 10 10 s max r l = 2 k; 0 pf < c l < 200 pf slew rate 1.5 1.5 1.5 v/s typ ? to ? scale capacitive load stability 2 2 2 nf typ r l = 10 10 10 nf typ r l = 2 k output noise spectral density 80 80 80 nv/hz typ dac code = midscale, 10 khz output noise (0.1 hz to 10 hz) 45 45 45 v p-p typ dac code = midscale digital-to-analog glitch impulse 5 5 5 nv-s typ 1 lsb change around major carry digital feedthrough 0.1 0.1 0.1 nv-s typ dc output impedance 0.5 0.5 0.5 typ short-circuit current 30 30 30 ma typ v dd = 5 v power-up time 5 5 5 s typ coming out of power-down mode; v dd = 5 v reference output output voltage 2.495 2.495 2.495 v min at ambient 2.505 2.505 2.505 v max reference tc 3 10 10 5 ppm/c typ 10 ppm/c max output impedance 7.5 7.5 7.5 k typ
ad5620/ad5640/ad5660 rev. f | page 4 of 28 parameter a grade 1 b grade 1 c grade 1 unit conditions/comments logic inputs 3 input current 2 2 2 a max all digital inputs v inl , input low voltage 0.8 0.8 0.8 v max v dd = 5 v v inh , input high voltage 2 2 2 v min v dd = 5 v pin capacitance 3 3 3 pf typ power requirements v dd 4.5 4.5 4.5 v min all digital inputs at 0 v or v dd 5.5 5.5 5.5 v max dac active and excluding load current i dd (normal mode) v dd = 4.5 v to 5.5 v 0.55 0.55 0.55 ma typ v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 1 1 1 ma max v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 4.5 v to 5.5 v 0.48 0.48 0.48 a typ v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 1 1 1 a max v ih = v dd and v il = gnd 1 temperature range is ?40c to +105c, typical at +25c. 2 linearity calculated using a reduced code range: ad5660 (code 511 to code 65024); ad5640 (code 128 to code 16256); ad5620 (cod e 32 to code 4064). output unloaded. linearity tested with v dd = 5.5 v. if part is operated with a v dd < 5 v, the output is clamped to v dd. 3 guaranteed by design and characterization; not production tested.
ad5620/ad5640/ad5660 rev. f | page 5 of 28 ad5620/ad5640/ad5660-1 v dd 1 = 2.7 v to 3.3 v, r l = 2 k to gnd, c l = 200 pf to gnd, c refout = 100 nf; all specifications t min to t max , unless otherwise noted. table 3. parameter a grade 2 b grade 2 c grade 2 unit conditions/comments static performance 3 ad5660 resolution 16 16 16 bits min relative accuracy 32 16 16 lsb max differential nonlinearity 1 1 1 lsb max guaranteed monotonic by design ad5640 resolution 14 14 14 bits min relative accuracy 8 4 4 lsb max differential nonlinearity 0.5 0.5 0.5 lsb max guaranteed monotonic by design ad5620 resolution 12 12 12 bits min relative accuracy 6 1 1 lsb max differential nonlinearity 0.25 0.25 0.25 lsb max guaranteed monotonic by design zero-code error 2 2 2 mv typ all 0s loaded to dac register 8 8 8 mv max offset error 9 9 9 mv max full-scale error 0.15 0.15 0.15 % fsr typ all 1s loaded to dac register 0.85 0.85 0.85 % fsr max gain error 0.85 0.85 0.85 % fsr max zero-code error drift 2 2 2 v/c typ gain temperature coefficient 2.5 2.5 2.5 ppm typ of fsr/c dc power supply rejection ratio ?60 ?60 ?60 db typ dac code = midscale; v dd = 3 v 10% output characteristics 4 output voltage range 0 0 v min v dd v dd v dd v max output voltage settling time 8 8 8 s typ ? to ? scale change settling to 2 lsb 10 10 10 s max r l = 2 k; 0 pf < c l < 200 pf slew rate 1.5 1.5 1.5 v/s typ ? to ? scale capacitive load stability 2 2 2 nf typ r l = 10 10 10 nf typ r l = 2 k output noise spectral density 80 80 80 nv/hz typ dac code = midscale, 10 khz output noise (0.1 hz to 10 hz) 20 20 20 v p-p typ dac code = midscale digital-to-analog glitch impulse 5 5 5 nv-s typ 1 lsb change around major carry digital feedthrough 0.1 0.1 0.1 nv-s typ dc output impedance 0.5 0.5 0.5 typ short-circuit current 30 30 30 ma typ v dd = 3 v power-up time 6 6 6 s typ coming out of power-down mode; v dd = 3 v reference output output voltage 1.247 1.247 1.247 v min at ambient 1.253 1.253 1.253 v max reference tc 4 10 10 5 ppm/c typ 15 ppm/c max output impedance 7.5 7.5 7.5 k typ
ad5620/ad5640/ad5660 rev. f | page 6 of 28 parameter a grade 2 b grade 2 c grade 2 unit conditions/comments logic inputs 4 input current 1 1 1 a max all digital inputs v inl , input low voltage 0.8 0.8 0.8 v max v dd = 3 v v inh , input high voltage 2 2 2 v min v dd = 3 v pin capacitance 3 3 3 pf max power requirements v dd 2.7 2.7 2.7 v min all digital inputs at 0 v or v dd 3.3 3.3 3.3 v max dac active and excluding load current i dd (normal mode) v dd = 2.7 v to 3.3 v 0.55 0.55 0.55 ma typ v ih = v dd and v il = gnd v dd = 2.7 v to 3.3 v 0.65 0.65 0.65 ma max v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 2.7 v to 3.3 v 0.2 0.2 0.2 a typ v ih = v dd and v il = gnd v dd = 2.7 v to 3.3 v 0.25 0.25 0.25 a max v ih = v dd and v il = gnd 1 part is functional with v dd up to 5.5 v. 2 temperature range is ?40c to +105c, typical at +25c. 3 linearity calculated using a reduced code range: ad5660 (code 511 to code 65024); ad5640 (code 128 to code 16256); ad5620 (cod e 32 to code 4064). output unloaded. 4 guaranteed by design and characterization; not production tested.
ad5620/ad5640/ad5660 rev. f | page 7 of 28 timing characteristics all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 2. v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 4. limit at t min , t max parameter v dd = 2.7 v to 3.6 v v dd = 3.6 v to 5.5 v unit conditions/comments t 1 1 50 33 ns min sclk cycle time t 2 13 13 ns min sclk high time t 3 13 13 ns min sclk low time t 4 13 13 ns min sync to sclk falling edge setup time t 5 5 5 ns min data setup time t 6 4.5 4.5 ns min data hold time t 7 0 0 ns min sclk falling edge to sync rising edge t 8 50 33 ns min minimum sync high time t 9 13 13 ns min sync rising edge to sclk fall ignore t 10 0 0 ns min sclk falling edge to sync fall ignore 1 maximum sclk frequency is 30 mhz at v dd = 3.6 v to 5.5 v and 20 mhz at v dd = 2.7 v to 3.6 v. din lsb = db0 msb = db23 for ad5660 msb = db15 for ad5620/ad5640 sync sclk msb lsb t 9 t 10 t 4 t 3 t 2 t 7 t 6 t 5 t 1 t 8 04539-002 figure 2. serial write operation
ad5620/ad5640/ad5660 rev. f | page 8 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v fb to gnd ?0.3 v to v dd + 0.3 v v refout to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c power dissipation (t j max ? t a )/ ja sot-23 package (4-layer board) ja thermal impedance 119c/w msop package (4-layer board) ja thermal impedance 141c/w jc thermal impedance 44c/w reflow soldering peak temperature snpb 240c pb-free 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5620/ad5640/ad5660 rev. f | page 9 of 28 pin configurations and function descriptions sync 04539-003 v dd 1 v refout 2 v fb 3 v out 4 gnd 8 din 7 sclk 6 5 ad5620/ ad5640/ ad5660 top view (not to scale) figure 3. sot-23 pin configuration sync 04539-004 v dd 1 v refout 2 v fb 3 v out 4 gnd 8 din 7 sclk 6 5 ad5620/ ad5640/ ad5660 top view (not to scale) figure 4. msop pin configuration table 6. pin function descriptions pin no. mnemonic description 1 v dd power supply input. these parts can operate from 2.7 v to 5.5 v. v dd should be decoupled to gnd. 2 v refout reference voltage output. 3 v fb feedback connection for the output amplifier. v fb should be connected to v out for normal operation. 4 v out analog output voltage from dac. the output amplifier has rail-to-rail operation. 5 sync level-triggered control input (active low). this is th e frame synchronization signal for the input data. when sync goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. the dac is updated following the 24 th clock cycle for the ad5660 and the 16 th clock cycle for ad5620/ad5640 unless sync is taken high before this edge. in this case, the rising edge of sync acts as an interrupt, and the write sequence is ignored by the dac. 6 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30 mhz. 7 din serial data input. the ad5660 has a 24-bit shift regi ster, and the ad5620/ad5640 have a 16-bit shift register. data is clocked into the register on the falling edge of the serial clock input. 8 gnd ground reference point for all circuitry on the part.
ad5620/ad5640/ad5660 rev. f | page 10 of 28 typical performance characteristics code inl error (lsb) 10 8 0 ?10 ?6 ?8 ?4 6 ?2 4 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 04539-005 figure 5. inlad5660-2/ad5660-3 code inl error (lsb) 4 3 ?4 ?3 ?2 2 ?1 1 0 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 04539-006 figure 6. inlad5640-2/ad5640-3 code inl error (lsb) 1.0 0.8 0 ?1.0 ?0.8 ?0.6 0.6 ?0.4 ?0.2 0.4 0.2 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 04539-007 figure 7. inlad5620-2/ad6520-3 code dnl error (lsb) 1.0 0.8 0 ?1.0 ?0.6 ?0.8 ?0.4 0.6 ?0.2 0.4 0.2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 04539-008 figure 8. dnlad5660-2/ad5660-3 code dnl error (lsb) 0.5 0.4 0 ?0.5 ?0.3 ?0.4 ?0.2 0.3 ?0.1 0.2 0.1 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 04539-009 figure 9. dnlad5640-2/ad5640-3 code dnl error (lsb) 0.20 0.15 0 ?0.20 ?0.15 ?0.10 0.10 ?0.05 0.05 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 04539-010 figure 10. dnlad5620-2/ad6520-3
ad5620/ad5640/ad5660 rev. f | page 11 of 28 code inl error (lsb) 10 8 4 6 2 0 ?4 ?2 ?6 ?8 ?10 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 04539-017 v dd = 3v v refout = 1.25v t a = 25 ?c figure 11. inlad5660-1 code inl error (lsb) 4 ?4 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 04539-018 3 2 1 0 ?1 ?2 ?3 v dd = 3v v refout = 1.25v t a = 25 ?c figure 12. inlad5640-1 code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 04539-019 0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 v dd = 3v v refout = 1.25v t a = 25 ?c figure 13. inlad5620-1 code dnl error (lsb) 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 04539-020 v dd = 3v v refout = 1.25v t a = 25 ?c figure 14. dnlad5660-1 code dnl error (lsb) 0.5 ?0.5 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 04539-021 0 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 v dd = 3v v refout = 1.25v t a = 25 ?c figure 15. dnlad5640-1 code dnl error (lsb) 0.20 ?0.20 0 500 1000 1500 2000 2500 3000 3500 4000 04539-025 0 0.15 0.10 0.05 ?0.05 ?0.10 ?0.15 v dd = 3v v refout = 1.25v t a = 25 ?c figure 16. dnlad5620-1
ad5620/ad5640/ad5660 rev. f | page 12 of 28 04539-011 ?40?200 20406080100 temperature (c) error (lsb) 12 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 max dnl max inl min dnl min inl v dd =5v figure 17. inl error and dnl error vs. temperature 04539-012 ?40 ?20 0 20 40 60 80 100 temperature (c) 0.4 ?0.4 ?0.2 0 0.2 error (%fsr) v dd =5v full scale error gain error figure 18. gain error and full-scale error vs. temperature 04539-013 ?40 ?20 0 20 40 60 80 100 temperature (c) 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 error (mv) v dd =5v zero code error offset error figure 19. zero-code and offset error vs. temperature i dd (ma) number of devices 200 180 160 140 100 120 80 20 40 60 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.65 0.64 0.66 0.67 04539-014 v dd = 5v t a = 25 ? c v dd = 3.3v figure 20. i dd histogram current (ma) error voltage (v) 0.50 0.40 ?0.50 ?0.40 ?0.30 ?0.20 ?0.10 0 0.10 0.20 0.30 ?10?8?6?4?2 0 2 4 8 610 04539-022 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v dac loaded with zero-scale sinking current dac loaded with full-scale sourcing current figure 21. headroom at rails vs. source and sink current (ma) v out (v) 6.00 5.00 4.00 3.00 2.00 1.00 ?1.00 0 ?30 ?20 ?10 0 10 20 30 04539-023 v dd = 5v v refout = 2.5v t a = 25 ?c zero scale full scale midscale 1/4 scale 3/4 scale figure 22. source and sink capabilityad5660-2/ad5660-3
ad5620/ad5640/ad5660 rev. f | page 13 of 28 current (ma) v out (v) 4.00 ?1.00 0 1.00 2.00 3.00 ?30 ?20 ?10 0 10 20 30 04539-024 v dd = 3v v refout = 1.25v t a = 25 ?c zero scale full scale midscale 1/4 scale 3/4 scale figure 23. source and sink capabilityad5660-1 code i dd (ma) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 512 20512 10512 30512 40512 50512 60512 04539-015 t a = 25 ?c v dd = 3v v dd = 5v figure 24. supply current vs. code v logic (v) i dd ( ? a) 1400 1200 1000 800 600 400 200 0 02 1345 04539-016 t a = 25 ?c v dd = 5v v dd = 3v figure 25. supply current vs. logic input voltage 04539-028 time base = 4 ? s/div v dd = 5v t a = 25 ?c full-scale code change 0x0000 to 0xffff output loaded with 2k? and 200pf to gnd v out = 909mv/div 1 figure 26. full-scale settling time, 5 v 04539-029 ch1 2.00v ch3 100mv ch2 2.00v m40.0ms ch1 v out v dd v ref 3 1 2 figure 27. power-on reset to 0 vad5660-2 04539-030 ch1 2.00v ch3 200mv ch2 2.00v m20.0 ? s ch1 1.88v v out v dd v ref 3 1 2 figure 28. power-on reset to midscalead5660-3
ad5620/ad5640/ad5660 rev. f | page 14 of 28 04539-031 ch1 1.20v ch3 100mv ch2 1.00v m100 ? s ch1 1.87v v out v dd v ref 3 1 2 figure 29. power-on reset to 0 vad5660-1 04539-055 ch1 2.00v ch3 50.0mv m1.00 ? s ch2 520mv v out v dd = 3v sclk 3 1 figure 30. exiting power-down to midscale sample number amplitude 2.501250 2.501000 2.500750 2.500500 2.500250 2.500000 2.499750 2.499500 2.499250 2.498750 2.499000 2.498500 2.498250 2.498000 0 150 200 250 50 100 300 350 400 450 500 550 04539-032 v dd = 5v v refout = 2.5v t a = 25 ?c 13ns/sample number 1lsb change around midscale (0x7fff to 0x8000) glitch impulse = 0.497nv-s figure 31. digital-to-analog glitch impulsead5660-2/ad5660-3 sample number amplitude 1.250800 1.250600 1.250400 1.250200 1.250000 1.249800 1.249600 1.249400 1.249200 1.249000 1.248800 1.248600 1.248400 0 150 200 250 50 100 300 350 400 450 500 550 04539-033 v dd = 3v v refout = 1.25v t a = 25 ?c 13ns/sample number 1lsb change around midscale (0x7fff to 0x8000) glitch impulse = 0.284nv-s figure 32. digital-to-analog glitch impulsead5660-1 sample number amplitude 2.500250 2.500200 2.500150 2.500100 2.500050 2.500000 2.499950 2.499900 2.499850 2.499800 2.499750 2.499700 2.499650 2.499600 0 150 200 250 50 100 300 350 400 450 500 550 04539-034 v dd = 5v t a = 25 ?c 20ns/sample number dac loaded with midscale digital feedthrough = 0.06nv-s figure 33. digital feedthrough capacitance (nf) time ( ? s) 16 14 12 10 8 6 4 012 34567 9 810 04539-036 t a = 25 ?c v dd = 5v v dd = 3v figure 34. settling time vs. capacitive load
ad5620/ad5640/ad5660 rev. f | page 15 of 28 5s/div 10 ? v/div 1 04539-037 v dd = 5v v refout = 2.5v t a = 25 ?c dac loaded with midscale figure 35. 0.1 hz to 10 hz output noisead5660-2/ad5660-3 4s/div 5 ? v/div 1 04539-054 v dd = 3v v refout = 1.25v t a = 25 ?c dac loaded with midscale figure 36. 0.1 hz to 10 hz output noisead5660-1 frequency (hz) output noise (nv ? hz) 800 0 100 200 300 400 500 600 700 100 10000 1000 100000 1000000 04539-038 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v t a = 25 ?c midscale loaded figure 37. noise spectral density
ad5620/ad5640/ad5660 rev. f | page 16 of 28 terminology relative accuracy for the dac, relative accuracy, or integral nonlinearity (inl), is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. figure 5 through figure 7 show typical inl vs. code. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. figure 8 through figure 10 show typical dnl vs. code. zero-code error zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5620/ad5640/ad5660, because the output of the dac cannot go below 0 v. it is due to a combination of the offset errors in the dac and the output amplifier. zero-code error is expressed in mv. figure 19 shows a plot of zero-code error vs. temperature. full-scale error full-scale error is a measurement of the output error when full- scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed as a percentage of the full-scale range. figure 18 shows a plot of full- scale error vs. temperature. gain error this is a measurement of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. zero-code error drift this is a measurement of the change in zero-code error with a change in temperature. it is expressed in v/c. gain temperature coefficient this is a measurement of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. offset error offset error is a measurement of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5660 with code 512 loaded into the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to the change in v dd for the full-scale output of the dac. it is measured in db. v ref is held at 2.5 v, and v dd is varied by 10%. output voltage settling time this indicates the amount of time for the output of a dac to settle to a specified level for a ? to ? full-scale input change. it is measured from the 24 th falling edge of sclk. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 31 and figure 32. digital feedthrough digital feedthrough is a measurement of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s or vice versa. noise spectral density this is a measurement of the internally generated random noise. random noise is characterized as a spectral density (voltage per hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. figure 37 shows a plot of noise spectral density.
ad5620/ad5640/ad5660 rev. f | page 17 of 28 theory of operation d/a section the ad5620/ad5640/ad5660 dacs are fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. the parts include an internal 1.25 v/2.5 v, 5 ppm/c reference that is internally gained up by 2. figure 38 shows a block diagram of the dac architecture. v dd r r v out gnd resistor string ref (+) ref (?) output amplifier dac register 04777-022 v fb figure 38. dac architecture because the input coding to the dac is straight binary, the ideal output voltage is given by uu n refout out d vv 2 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register. 0 to 4095 for ad5620 (12 bit) 0 to 16383 for ad5640 (14 bit) 0 to 65535 for ad5660 (16 bit) n is the dac resolution. r r r r r to output amplifier 04539-040 figure 39. resistor string resistor string the resistor string section is shown in figure 39. it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. internal reference the ad5620/ad5640/ad5660-1 parts include an internal, 1.25 v, 5 ppm/c reference, giving a full-scale output voltage of 2.5 v. the ad5620/ad5640/ad5660-2-3 parts include an internal, 2.5 v, 5 ppm/c reference, giving a full-scale output voltage of 5 v. the reference associated with each part is available at the v refout pin. a buffer is required if the reference output is used to drive external loads. it is recommended that a 100 nf capacitor is placed between the reference output and gnd for reference stability. output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . this output buffer amplifier has a gain of 2 derived from a 50 k resistor divider network in the feedback path. the inverting input of the output amplifier is available to the user, allowing for remote sensing. this v fb pin must be connected to v out for normal operation. it can drive a load of 2 k in parallel with 1000 pf to gnd. figure 21 shows the source and sink capabilities of the output amplifier. the slew rate is 1.5 v/s with a ? to ? full- scale settling time of 10 s. serial interface the ad5620/ad5640/ad5660 have a 3-wire serial interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as most dsps. see figure 2 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the din line is clocked into the 16-bit shift register (ad5620/ad5640) or the 24-bit shift register (ad5660) on the falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making the ad5620/ad5640/ad5660 compatible with high speed dsps. on the 16 th falling clock edge (ad5620/ ad5640) or the 24th falling clock edge (ad5660), the last data bit is clocked in and the programmed function is executed, that is, a change in the dac register contents and/or a change in the mode of operation is executed. at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 2 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation of the parts. as is mentioned previously, however, sync must be brought high again just before the next write sequence.
ad5620/ad5640/ad5660 rev. f | page 18 of 28 input shift register ad5620/ad5640 the input shift register is 16 bits wide for the ad5620/ad5640 (see figure 40 and figure 41). the first two bits are control bits that control which mode of operation the part is in (normal mode or any of the three power-down modes). the next 14/12 bits, respectively, are the data bits. these are transferred to the dac register on the 16 th falling edge of sclk. ad5660 the input shift register is 24 bits wide for the ad5660 (see figure 42). the first six bits are dont care bits. the next two are control bits that control which mode of operation the part is in (normal mode or any of the three power-down modes). for a more complete description of the various modes, see the power-down modes section. the next 16 bits are the data bits. these are transferred to the dac register on the 24 th falling edge of sclk. sync interrupt in a normal write sequence for the ad5660, the sync line is kept low for at least 24 falling edges of sclk, and the dac is updated on the 24 th falling edge. however, if sync is brought high before the 24 th falling edge, this acts as an interrupt to the write sequence. the shift register is reset, and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see figure 43). similarly, in a normal write sequence for the ad5620/ad5640, the sync line is kept low for at least 16 falling edges of sclk, and the dac is updated on the 16 th falling edge. however, if sync is brought high before the 16 t h falling edge, this acts as an interrupt to the write sequence. data bits db15 (msb) db0 (lsb) pd1 pd0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x 04539-041 figure 40. ad5620 input register contents data bits db15 (msb) db0 (lsb) pd1 pd0 d11 d10 d13 d12 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 04539-042 figure 41. ad5640 input register contents data bits db23 (msb) db0 (lsb) pd1 pd0 d15 d14 d13 d12 x x x x x x d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 04539-043 figure 42. ad5660 input register contents 04539-044 din msb msb lsb lsb invalid write sequence: sync high before 16 th /24 th falling edge valid write sequence, output updates on the 16 th /24 th falling edge sync sclk figure 43. sync interrupt facility
ad5620/ad5640/ad5660 rev. f | page 19 of 28 power-on reset the ad5620/ad5640/ad5660 family contains a power-on reset circuit that controls the output voltage during power-up. the ad5620/ad5640/ad5660-1-2 dac output powers up to 0 v, and the ad5620/ad5660-3 dac output powers up to midscale. the output remains at this level until a valid write sequence is made to the dac, which is useful in applications where it is important to know the state of the dac output while it is in the process of powering up. power-down modes the ad5620/ad5640/ad5660 have four separate modes of operation. these modes are software-programmable by setting two bits in the control register. table 7 and table 8 show how the state of the bits corresponds to the operating mode of the device. table 7. modes of operation for the ad5660 db17 db16 ad5660 operating mode 0 0 normal operation power-down modes: 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three-state table 8. modes of operation for the ad5620/ad5640 db15 db14 ad5620/ad5640 operating mode 0 0 normal operation power-down modes: 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three-state when both bits are set to 0, the part works normally with its normal power consumption of 550 a at 5 v. however, for the three power-down modes, the supply current falls to 480 na at 5 v (200 na at 3 v). not only does the supply current fall, but the output stage is internally switched from the output of the amplifier to a resistor network of known values. the advan- tage is that the output impedance of the part is known while the part is in power-down mode. there are three options: the out- put is connected internally to gnd through a 1 k or a 100 k resistor, or it is left open-circuited (three-stated). the output stage is shown in figure 44. resistor network v out resistor string dac 04539-045 power-down circuitry amplifier figure 44. output stage during power-down the bias generator, output amplifier, reference, resistor string, and other associated linear circuitry are all shut down when power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power-down is typically 5 s for v dd = 5 v and v dd = 3 v (see figure 30). microprocessor interfacing ad5660-to-blackfin? adsp-bf53x interface figure 45 shows a serial interface between the ad5660 and the blackfin adsp-bf53x microprocessor. the adsp-bf53x processor family incorporates two dual-channel synchronous serial ports, sport1 and sport0, for serial and multi- processor communications. using sport0 to connect to the ad5660, the setup for the interface is as follows: dt0pri drives the din pin of the ad5660, while tsclk0 drives the sclk of the part and sync is driven from tfs0. ad5660 1 1 additional pins omitted for clarity tfs0 dtopri tsclk0 sync din sclk 04539-046 adsp-bf53x 1 figure 45. ad5660-to-blackfin adsp-bf53x interface
ad5620/ad5640/ad5660 rev. f | page 20 of 28 ad5660-to-68hc11/68l11 interface figure 46 shows a serial interface between the ad5660 and the 68hc11/68l11 microcontroller. sck of 68hc11/68l11 drives the sclk of ad5660, and the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 should be con- figured so that its cpol bit is 0, and its cpha bit is 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured in this way, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5660, pc7 is left low after the first eight bits are transferred, a second serial write operation is performed to the dac, and pc7 is taken high at the end of this procedure. ad5660 1 1 additional pins omitted for clarity pc7 sck mosi sync sclk din 04539-047 68hc11/68l11 1 figure 46. ad5660-to-68hc11/68l11 interface ad5660-to-80c51/80l51 interface figure 47 shows a serial interface between the ad5660 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5660, and rxd drives the serial data line of the part. the sync signal is again derived from a bit-programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5660, p3.3 is taken low. the 80c51/80l51 transmit data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 output the serial data lsb first; however, the ad5660 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. 80c51/80l51 1 ad5660 1 p3.3 txd rxd sync sclk din 04539-048 1 additional pins omitted for clarity figure 47. ad5660-to-80c51/80l51 interface ad5660-to-microwire interface figure 48 shows an interface between the ad5660 and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5660 on the rising edge of the sk. microwire 1 ad5660 1 cs sk so sync sclk din 04539-049 1 additional pins omitted for clarity figure 48. ad5660-to-microwire interface
ad5620/ad5640/ad5660 rev. f | page 21 of 28 applications information using a ref19x as a power supply for the ad5620/ad5640/ad5660 because the supply current required by the ad5620/ad5640/ ad5660 is extremely low, an alternative option is to use a ref19x voltage reference (ref195 for 5 v or ref193 for 3 v) to supply the required voltage to the part (see figure 49). this is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the ref19x outputs a steady supply voltage for the ad5620/ ad5640/ad5660. if the low dropout ref195 is used, the current it needs to supply to the ad5660 is 500 a. this is with no load on the output of the dac. when the dac output is loaded, the ref195 also must supply the current to the load. the total current required (with a 5 k load on the dac output) is 500 a + (5 v/5 k) = 1.5 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 3 ppm (15 v) for the 1.5 ma current drawn from it. this corresponds to a 0.197 lsb error for the ad5660. ad5660 3-wire serial interface sync sclk din 15v 5v v out = 0v to 5v ref195 04539-050 figure 49. ref195 as the power supply to the ad5660 bipolar operation using the ad5660 the ad5660 is designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 50. figure 50 gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? r1 r2 v r1 r2r1d vv dd dd o 65536 where d represents the input code in decimal (0 to 65535). when v dd = 5 v, r1 = r2 = 10 k, v5 65536 10 ? ? ? ? ? ? ? ? ? d v o this results in an output voltage range of 5 v, with 0x0000 corresponding to a ?5 v output and 0xffff corresponding to a +5 v output. r2 10k ? 04539-051 +5v ?5v ad820/ op295 3-wire serial interface +5v ad5660 v dd v fb v out r1 10k ? 5v 0.1? f 10 ? f figure 50. bipolar operation with the ad5660
ad5620/ad5640/ad5660 rev. f | page 22 of 28 04539-052 serial load ad5660 v loop 12v to 36v 4?20ma ad8627 r1 4.7k ? r2 18.5k ? p1 20ma adjust p2 4ma adjust r6 3.3k ? r3 1.5k ? d1 q1 2n3904 r7 100 ? rl adr02 figure 51. programmable 4 ma to 20 ma process controller using the ad5660 as an isolated, programmable, 4 ma to 20 ma process controller in many process-control system applications, 2-wire current transmitters are used to transmit analog signals through noisy environments. these current transmitters use a zero-scale signal current of 4 ma to power the signal conditioning circuitry of the transmitter. the full-scale output signal in these transmitters is 20 ma. the converse approach to process control can also be used, in which a low-power, programmable current source is used to control remotely located sensors or devices in the loop. a circuit that performs this function is shown in figure 51. using the ad5660 as the controller, the circuit provides a programmable output current of 4 to 20 ma, proportional to the digital code of the dac. biasing for the controller is provided by the adr02 and requires no external trim for two reasons: first, the adr02s tight initial output voltage tolerance, and second, the low supply current consumption of both the ad8627 and the ad5660. the entire circuit, including optocouplers, consumes less than 3 ma from the total budget of 4 ma. the ad8627 regulates the output current to satisfy the current summation at the noninverting node of the ad8627. i out = 1/ r7 ( v dac r3 / r1 + v ref r3 / r2 ) for the values shown in figure 51, i out = 0.2435 a d + 4 ma where d = 0 d 65,535, giving a full-scale output current of 20 ma when the ad5660s digital code equals 0xffff. offset trim at 4 ma is provided by p2, and p1 provides the circuit gain trim at 20 ma. these two trims do not interact because the noninverting input of the ad8627 is at virtual ground. the schottky diode, d1, is required in this circuit to prevent loop supply power-on transients from pulling the noninverting input of the ad8627 more than 300 mv below its inverting input. without this diode, such transients could cause phase reversal of the ad8627 and possible latch-up of the controller. the loop supply voltage compliance of the circuit is limited by the maximum applied input voltage to the adr02 and is from 12 v to 40 v. using the ad5620/ad5640/ad5660 with a galvanically isolated interface for process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from hazardous common-mode voltages that might occur in the area where the dac is functioning. the i coupler? provides isolation in excess of 2.5 kv. the ad5620/ad5640/ad5660 use a 3-wire serial logic interface; therefore, the adum1300 3-channel digital isolator provides the required isolation (see figure 52). the power supply to the part also must be isolated, which is done by using a transformer. on the dac side of the trans- former, a 5 v regulator provides the 5 v supply required for the ad5620/ad5640/ad5660. 0.1 ? f 5v regulator gnd 04539-053 din sync sclk power 10 ? f sdi sclk data ad56x0 v out v ob v oa v oc v dd v 1c v 1b v 1a adum1300 figure 52. ad5620/ad5640/ad5660 with a galvanically isolated interface
ad5620/ad5640/ad5660 rev. f | page 23 of 28 power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5620/ ad5640/ad5660 should have separate analog and digital sections, each having its own area of the board. if the ad5620/ ad5640/ad5660 are in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5620/ad5640/ad5660. the power supply to the ad5620/ad5640/ad5660 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be as close as physically possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has a low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other components with fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. the best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2-layer board.
ad5620/ad5640/ad5660 rev. f | page 24 of 28 outline dimensions compliant to jedec standards mo-178-ba 8 4 0 seating plane 1.95 bsc 0.65 bsc 0.60 bsc 76 1234 5 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.22 max 0.08 min 0.38 max 0.22 min 0.60 0.45 0.30 pin 1 indicator 8 12-16-2008-a figure 53. 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 54. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ad5620/ad5640/ad5660 rev. f | page 25 of 28 ordering guide model 1 temperature range package description package option branding power-on reset to code accuracy internal reference ad5620arj-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2k zero 6 lsb inl 1.25 v ad5620arjz-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 d6v zero 6 lsb inl 1.25 v ad5620arj-1reel7 ?40c to +105c 8-lead sot-23 rj-8 d2k zero 6 lsb inl 1.25 v ad5620arj-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2l zero 6 lsb inl 2.5 v ad5620arjz-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d5d zero 6 lsb inl 2.5 v ad5620arj-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d2l zero 6 lsb inl 2.5 v ad5620arjz-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d5d zero 6 lsb inl 2.5 v ad5620armz-2 ?40c to +105c 8-lead msop rm-8 dgy zero 6 lsb inl 2.5 v ad5620armz-2reel7 ?40c to +105c 8-lead msop rm-8 dgy zero 6 lsb inl 2.5 v ad5620brj-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2h zero 1 lsb inl 1.25 v ad5620brjz-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 d87 zero 1 lsb inl 1.25 v ad5620brj-1reel7 ?40c to +105c 8-lead sot-23 rj-8 d2h zero 1 lsb inl 1.25 v ad5620brj-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2j zero 1 lsb inl 2.5 v ad5620brjz-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d5c zero 1 lsb inl 2.5 v ad5620brj-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d2j zero 1 lsb inl 2.5 v ad5620brjz-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d5c zero 1 lsb inl 2.5 v ad5620crm-1 ?40c to +105c 8-lead msop rm-8 d2m zero 1 lsb inl 1.25 v ad5620crmz-1 ?40c to +105c 8-lead msop rm-8 dgm zero 1 lsb inl 1.25 v ad5620crm-1reel7 ?40c to +105c 8-lead msop rm-8 d2m zero 1 lsb inl 1.25 v ad5620crmz-1reel7 ?40c to +105c 8-lead msop rm-8 dgm zero 1 lsb inl 1.25 v ad5620crm-2 ?40c to +105c 8-lead msop rm-8 d2n zero 1 lsb inl 2.5 v ad5620crm-2reel7 ?40c to +105c 8-lead msop rm-8 d2n zero 1 lsb inl 2.5 v ad5620crmz-2 ?40c to +105c 8-lead msop rm-8 d59 zero 1 lsb inl 2.5 v ad5620crmz-2reel7 ?40c to +105c 8-lead msop rm-8 d59 zero 1 lsb inl 2.5 v ad5620crm-3 ?40c to +105c 8-lead msop rm-8 d2p midscale 1 lsb inl 2.5 v ad5620crmz-3 ?40c to +105c 8-lead msop rm-8 dgn midscale 1 lsb inl 2.5 v ad5620crm-3reel7 ?40c to +105c 8-lead msop rm-8 d2p midscale 1 lsb inl 2.5 v ad5620crmz-3reel7 ?40c to +105c 8-lead msop rm-8 dgn midscale 1 lsb inl 2.5 v eval-ad5620ebz evaluation board ad5640arj-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2t zero 8 lsb inl 2.5 v ad5640arjz-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 dc6 zero 8 lsb inl 2.5 v ad5640arj-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d2t zero 8 lsb inl 2.5 v ad5640arjz-2reel7 ?40c to +105c 8-lead sot-23 rj-8 dc6 zero 8 lsb inl 2.5 v ad5640brj-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2q zero 4 lsb inl 1.25 v ad5640brjz-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 dc3 zero 4 lsb inl 1.25 v ad5640brj-1reel7 ?40c to +105c 8-lead sot-23 rj-8 d2q zero 4 lsb inl 1.25 v ad5640brjz-1reel7 ?40c to +105c 8-lead sot-23 rj-8 dc3 zero 4 lsb inl 1.25 v ad5640brj-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2r zero 4 lsb inl 2.5 v ad5640brjz-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 dc0 zero 4 lsb inl 2.5 v ad5640brj-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d2r zero 4 lsb inl 2.5 v ad5640brjz-2reel7 ?40c to +105c 8-lead sot-23 rj-8 dc0 zero 4 lsb inl 2.5 v ad5640crm-1 ?40c to +105c 8-lead msop rm-8 d2u zero 4 lsb inl 1.25 v ad5640crm-1reel7 ?40c to +105c 8-lead msop rm-8 d2u zero 4 lsb inl 1.25 v ad5640crmz-1 ?40c to +105c 8-lead msop rm-8 dg1 zero 4 lsb inl 1.25 v ad5640crmz-1reel7 ?40c to +105c 8-lead msop rm-8 dg1 zero 4 lsb inl 1.25 v ad5640crm-2 ?40c to +105c 8-lead msop rm-8 d2v zero 4 lsb inl 2.5 v ad5640crm-2reel7 ?40c to +105c 8-lead msop rm-8 d2v zero 4 lsb inl 2.5 v ad5640crmz-2 ?40c to +105c 8-lead msop rm-8 dew zero 4 lsb inl 2.5 v ad5640crmz-2reel7 ?40c to +105c 8-lead msop rm-8 dew zero 4 lsb inl 2.5 v
ad5620/ad5640/ad5660 rev. f | page 26 of 28 model 1 temperature range package description package option branding power-on reset to code accuracy internal reference ad5660arj-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 d30 zero 32 lsb inl 1.25 v AD5660ARJZ-1500RL7 ?40c to +105c 8-lead sot-23 rj-8 d5g zero 32 lsb inl 1.25 v ad5660arj-1reel7 ?40c to +105c 8-lead sot-23 rj-8 d30 zero 32 lsb inl 1.25 v ad5660arjz-1reel7 ?40c to +105c 8-lead sot-23 rj-8 d5g zero 32 lsb inl 1.25 v ad5660arj-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d31 zero 32 lsb inl 2.5 v ad5660arjz-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d6k zero 32 lsb inl 2.5 v ad5660arj-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d31 zero 32 lsb inl 2.5 v ad5660arjz-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d6k zero 32 lsb inl 2.5 v ad5660arj-3500rl7 ?40c to +105c 8-lead so t-23 rj-8 d32 midscale 32 lsb inl 2.5 v ad5660arjz-3500rl7 ?40c to +105c 8-lead sot-23 rj-8 dav midscale 32 lsb inl 2.5 v ad5660arj-3reel7 ?40c to +105c 8-lead so t-23 rj-8 d32 midscale 32 lsb inl 2.5 v ad5660arjz-3reel7 ?40c to +105c 8-lead so t-23 rj-8 dav midscale 32 lsb inl 2.5 v ad5660brj-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2x zero 16 lsb inl 1.25 v ad5660brjz-1500rl7 ?40c to +105c 8-lead sot-23 rj-8 d6c zero 16 lsb inl 1.25 v ad5660brj-1reel7 ?40c to +105c 8-lead sot-23 rj-8 d2x zero 16 lsb inl 1.25 v ad5660brjz-1reel7 ?40c to +105c 8-lead sot-23 rj-8 d6c zero 16 lsb inl 1.25 v ad5660brj-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d2y zero 16 lsb inl 2.5 v ad5660brjz-2500rl7 ?40c to +105c 8-lead sot-23 rj-8 d6l zero 16 lsb inl 2.5 v ad5660brj-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d2y zero 16 lsb inl 2.5 v ad5660brjz-2reel7 ?40c to +105c 8-lead sot-23 rj-8 d6l zero 16 lsb inl 2.5 v ad5660brj-3500rl7 ?40c to +105c 8-lead so t-23 rj-8 d2z midscale 16 lsb inl 2.5 v ad5660brjz-3500rl7 ?40c to +105c 8-lead so t-23 rj-8 dan midscale 16 lsb inl 2.5 v ad5660brj-3reel7 ?40c to +105c 8-lead so t-23 rj-8 d2z midscale 16 lsb inl 2.5 v ad5660brjz-3reel7 ?40c to +105c 8-lead so t-23 rj-8 dan midscale 16 lsb inl 2.5 v ad5660crm-1 ?40c to +105c 8-lead msop rm-8 d33 zero 16 lsb inl 1.25 v ad5660crm-1reel7 ?40c to +105c 8-lead msop rm-8 d33 zero 16 lsb inl 1.25 v ad5660crmz-1 ?40c to +105c 8-lead msop rm-8 dex zero 16 lsb inl 1.25 v ad5660crmz-1reel7 ?40c to +105c 8-lead msop rm-8 dex zero 16 lsb inl 1.25 v ad5660crm-2 ?40c to +105c 8-lead msop rm-8 d34 zero 16 lsb inl 2.5 v ad5660crm-2reel7 ?40c to +105c 8-lead msop rm-8 d34 zero 16 lsb inl 2.5 v ad5660crmz-2 ?40c to +105c 8-lead msop rm-8 dey zero 16 lsb inl 2.5 v ad5660crmz-2reel7 ?40c to +105c 8-lead msop rm-8 dey zero 16 lsb inl 2.5 v ad5660crm-3 ?40c to +105c 8-lead msop rm-8 d35 midscale 16 lsb inl 2.5 v ad5660crm-3reel7 ?40c to +105c 8-lead msop rm-8 d35 midscale 16 lsb inl 2.5 v ad5660crmz-3 ?40c to +105c 8-lead msop rm-8 dby midscale 16 lsb inl 2.5 v ad5660crmz-3reel7 ?40c to +105c 8-lead msop rm-8 dby midscale 16 lsb inl 2.5 v eval-ad5660ebz evaluation board eval-ad5660dkz demonstration board 1 z = rohs compliant part.
ad5620/ad5640/ad5660 rev. f | page 27 of 28 notes
ad5620/ad5640/ad5660 rev. f | page 28 of 28 notes ?2005C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04539-0-1 2/ 10(f)

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